A memory controller, also known as memory chip controller (MCC) or a memory controller unit (MCU), is a digital circuit that manages the flow of information going to and from a pc's predominant memory. When a memory controller is integrated into another chip, equivalent to an integral a part of a microprocessor, it's normally known as an integrated memory controller (IMC). Memory controllers include the logic essential to read and write to dynamic random-entry memory (DRAM), and to supply the critical memory refresh and different features. Reading and writing to DRAM is carried out by choosing the row and column knowledge addresses of the DRAM as the inputs to the multiplexer circuit, where the demultiplexer on the DRAM makes use of the converted inputs to pick the proper memory location and return the info, which is then passed again via a multiplexer to consolidate the data in order to scale back the required bus width for the operation. Memory controllers' bus widths vary from 8-bit in earlier methods, to 512-bit in more difficult methods, the place they are typically applied as 4 64-bit simultaneous memory controllers working in parallel, though some function with two 64-bit memory controllers getting used to entry a 128-bit memory gadget.

Some memory controllers, such as the one integrated into PowerQUICC II processors, embody error detection and correction hardware. Many trendy processors are additionally built-in memory administration unit (MMU), which in lots of working programs implements virtual addressing. On early x86-32 processors, the MMU is integrated in the CPU, however the memory controller is usually part of northbridge. Older Intel and PowerPC-primarily based computer systems have memory controller chips which can be separate from the main processor. Often these are built-in into the northbridge of the computer, also generally known as a memory controller hub. Most fashionable desktop or Memory Wave workstation microprocessors use an built-in memory controller (IMC), together with microprocessors from Intel, AMD, and those constructed around the ARM architecture. Previous to K8 (circa 2003), AMD microprocessors had a memory controller carried out on their motherboard's northbridge. In K8 and later, AMD employed an built-in memory controller. Likewise, till Nehalem (circa 2008), Intel microprocessors used memory controllers implemented on the motherboard's northbridge.

Nehalem and later switched to an integrated memory controller. Other examples of microprocessor architectures that use built-in memory controllers embody NVIDIA's Fermi, IBM's POWER5, and Solar Microsystems's UltraSPARC T1. Whereas an integrated memory controller has the potential to extend the system's performance, equivalent to by lowering memory latency, it locks the microprocessor to a specific sort (or varieties) of memory, forcing a redesign as a way to help newer memory applied sciences. When DDR2 SDRAM was introduced, MemoryWave AMD released new Athlon sixty four CPUs. These new fashions, with a DDR2 controller, use a different physical socket (referred to as Socket AM2), in order that they may solely slot in motherboards designed for the new sort of RAM. When the memory controller is not on-die, the identical CPU could also be installed on a brand new motherboard, with an up to date northbridge to use newer memory. Some microprocessors in the nineteen nineties, such because the DEC Alpha 21066 and HP PA-7300LC, had built-in memory controllers; nonetheless, moderately than for performance positive factors, this was implemented to reduce the cost of systems by eliminating the need for an external memory controller.

Some CPUs are designed to have their memory controllers as dedicated exterior parts that are not a part of the chipset. An example is IBM POWER8, which uses external Centaur chips that are mounted onto DIMM modules and act as memory buffers, L4 cache chips, and because the precise memory controllers. The first model of the Centaur chip used DDR3 memory however an updated version was later launched which may use DDR4. A number of experimental memory controllers contain a second degree of handle translation, in addition to the first degree of tackle translation carried out by the CPU's memory administration unit to improve cache and bus efficiency. Memory controllers integrated into sure Intel Core processors provide memory scrambling as a characteristic that turns person knowledge written to the main memory into pseudo-random patterns. Memory scrambling has the potential to prevent forensic and reverse-engineering evaluation based on DRAM knowledge remanence by successfully rendering varied kinds of chilly boot attacks ineffective.

In present practice, this has not been achieved; memory scrambling has solely been designed to address DRAM-related electrical issues. The late 2010s memory scrambling requirements do address security issues and are not cryptographically secure or open to public revision or evaluation. ASUS and Intel have their separate memory scrambling requirements. ASUS motherboards have allowed the person to choose which memory scrambling customary to use (ASUS or Intel) or whether or not to turn the characteristic off fully. Double knowledge fee (DDR) memory controllers are used to drive DDR SDRAM, where knowledge is transferred on each rising and falling edges of the system's memory clock. Multichannel memory controllers are memory controllers the place the DRAM devices are separated onto multiple buses to allow the memory controller(s) to access them in parallel. This will increase the theoretical amount of bandwidth of the bus by an element of the variety of channels. Whereas a channel for each DRAM can be the ideal answer, including extra channels will increase complexity and value.